Computer Organization and Architecture GATE Questions - Year 2001 and 2002

This post covers the computer organization and architecture GATE questions with solution. These questions are based on the concepts from computer system architecture by morris mano book. gate csc.

Computer Organization and Architecture GATE Questions - Year 2001 and 2002


Question. 1. More than one word are put in one cache block to

(A) Exploit the temporal locality of reference in a program
(B) Exploit the spatial locality of reference in a program
(C) Reduce the miss penalty
(D) None of the above.

Question. 2.A CPU has two modes-privileged and non-privileged. In order to
change the mode from privileged to non-privileged.

(A) A hardware interrupt is needed.
 (B) A software interrupt is needed.
(C) A privileged instruction (which does not generate an interrupt) is needed.
(D) A non-privileged instruction (Which does not generate an
interrupt) is needed.

Question. 3.Suppose a processor does not have any stack pointer register. Which of the following statements is true ?

(A) It cannot have subroutine call instruction
(B) It can have subroutine call instruction, but no nested subroutine calls.
(C) Nested subroutine calls are possible, but interrupts are not.
(D) All sequences of subroutine calls and also interrupts are possible

Question.4. Which is the most appropriate match for the items in the first column with the items in the second column.

(X.) Indirect Addressing                         (I.) Array implementation
(Y.) Indexed Addressing                         (II.) Writing re-locatable code
(Z.) Base Register Addressing                (III.) Passing array as parameter

(A) (X, III) (Y, I) (Z, II) (B) (X, II) (Y, III) (Z, I)
(C) (X, III) (Y, II) (Z, I) (D) (X, I) (Y, III) (Z, II)

Question.5. A processor needs software interrupt to

(A) Test the interrupt system of the processor.
(B) Implement co-routines.
(C) Obtain system services which need execution of privileged instructions.
(D) Return from subroutine.

Question.6.The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called

(A) Assembly (B) Parsing
(C) Relocation (D) Symbol resolution.

 Question.7. Which of the following requires a device driver ?

(A) Register (B) Cache
(C) Main memory (D) Disk.

Question.8.Which of the following does not interrupt a running process ?

(A) A device (B) Timer
(C) Scheduler process (D) Power failure

Question. 9. Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8#(2:1) and the DEMUX is of size 8#(1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally. The CPU instruction “push r”, where = A or B, has the specification 

M[SP] !r

SP ! SP − 1

How many CPU clock cycles are needed to execute the “push r” instruction ?

(A) 2 (B) 3
(C) 4 (D) 5


coa previous year gate questions with answer


Question.10. A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

(A) INTA is active (B) HOLD is active
(C) READY is active (D) None of the above

Question.11.In 8085 which of the following modifies the program counter ?

(A) Only PCHL instruction
(B) Only ADD instructions
(C) Only JMP and CALL instructions
(D) All instructions.

Question.12.In serial data transmission, every byte of data is padded with a ‘0’ in the beginning and one or two ‘1’s at the end of byte because

(A) Receiver is to be synchronized for byte reception
(B) Receiver recovers lost ‘0’s and ‘1’ from these padded bits
(C) Padded bits are useful in parity computation.
(D) None of the above

Question. 13. Which of the following is not a form of memory ?

(A) Instruction cache (B) Instruction register
(C) Instruction opcode (D) Translation-a-side buffer

Question 14.In the C language

(A) At most one activation record exists between the current activation record and the activation record for the main.

(B) The number of activation records between the current activation record and the activation record for the main depends on the actual function calling sequence.

(C) The visibility of global variables depends on the actual function calling sequence.

(D) Recursion requires the activation record for the recursive function to be saved on a different stack before the recursive fraction can be called.

Question. 15. Horizontal micro programming

(A) Does not require use of signal decoders
(B) Results in larger sized micro instructions than vertical micro programming
(C) Uses one bit for each control signal

(D) All of the above.

Question. 16 . The performance of a pipelined processor suffers if

(A) The pipelined stages have different delays
(B) Consecutive instructions are dependent on each other
(C) The pipeline stages share hardware resources
(D) All the above.

Question 17. In the absolute the addressing mode.

(A) The operand is inside the instruction
(B) The address of the operand is inside the instruction
(C) The register containing the address of the operand is specified.
(D) The location of the operand is implicit.

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Computer Science Junction: Computer Organization and Architecture GATE Questions - Year 2001 and 2002
Computer Organization and Architecture GATE Questions - Year 2001 and 2002
This post covers the computer organization and architecture GATE questions with solution. These questions are based on the concepts from computer system architecture by morris mano book. gate csc.
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