Computer Organization and Architecture - Practice Set 3 Solution

COMPUTER ORGANIZATION AND ARCHITECTURE (Instruction Pipelining, Cache & Main memory, Secondary Storage) PRACTICE SET 3 - SOLUTI...


COMPUTER ORGANIZATION AND ARCHITECTURE
(Instruction Pipelining, Cache & Main memory, Secondary Storage)

PRACTICE SET 3 - SOLUTIONS

1. More than one word is put in one cache block to
(a) Exploit temporal locality references in a program
(b) Exploit spatial locality references in a program
(c) Reduce miss penalty
(d) All of these

Solution: Option (b)

2. A pipeline P is found to provide a speedup of 6.16 when operating at 100 MHz and an efficiency of 88 percent. How many stages does P have?

Solution: From 7.21 To 6.79

Explanation: Clock Time=10ns, 88100[p×1010]=6.16, p=7

3. How big is a four way set associative cache memory with a block size of 64 Bytes and containing 1024 sets?

Solution: From 263.68 To 248.32

Explanation:
1024 × 4 × 64 Bytes = 218 = 256 Kbytes

4. A five stage pipeline has a clock cycle time of 5ns. If the non-pipeline clock is also of the same duration than what is the speed up for 75% of pipeline efficiency?

Solution: From 3.863 To 3.638
Explanation:
Non-pipeline: 5 × 5 = 25
Pipeline – 5 For 100%−255=5 For 75%−75100×5=3.75

5. A tiny bootstrap loader program is situated in
(a) Hard disk (b) ROM
(c) BIOS (d) None of these
Solution: Option (b)

6. If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving an average memory access of 2 cycles (in %)?

Solution: From 82.4 To 77.6

Explanation:
2 cycle average access = (1 cycle for cache) + (1 – hit rate) (5 cycles stall) ⇒ hit rate = 80%

7. Cache and word addressable main memory system has the following specification
Cache block size = 16 words
Set size = 2 blocks
Number of sets = 128
Number of bits in a word = 32 bits
Cache access time (Tc) = 20ns
Memory access (Tm) = 120ns
Hit (H) = 0.8
Size of main memory address = 21bits

What is the total cache size needed?
(a) (16k + 140) bytes (b) (16k + 320) bytes
(c) (256k + 180) bytes (d) (60k + 300) bytes
Solution: Option (b)
Explanation:
Total size of cache=128×2×16×328 + 128×2×108
128 set, each set 2 block 128 set, each set 2 block
each block 16 word, each block 16 word,
each word 32 bit each word 32 bit
27×2×24×2523+16×2×10=(16K+320)byte

8. Consider a machine with 10ns clock and it takes 4 clock cycle per ALU instruction, 5 clock cycle per branch instruction, 6 clock cycle memory instruction. There exists 40% ALU instruction, 20% branch instruction and 40% memory instruction.

What is throughput of pipeline system if overhead is 2ns?
(a) 83MIPS (b) 84MIPS
(c) 85MIPS (d) 86MIPS

Solution: Option (a)
Explanation:
Average access time for non-pipeline system [4×.40+5×.20+.40×6]×10ns=[1.6+1+2.4]×10ns=5×10ns=50ns
For pipeline system in every clock cycle one instruction will get executed and overhead of 2 nano sec.
So, average time = (10 + 2) ns = 12 ns,
throughput of system 112ns=83 MIPS

9. A 5 stage pipeline has the stages IF, ID, OF, PO, WB (Assume that there are no separate data and instruction caches). For the program below, what is/are the hazard(s) possible? MOV R1,A; R1←μ[A]
MOV R2,A; R2←μ[B] ADD R1,R2; R1←R1+R2 MOV X,R1; μ[x]←R1
(a) Data Hazard (b) Structural Hazard
(c) Control Hazard (d) Both (a) & (b)

Solution: Option (b)

10. An instruction pipeline consists of 4 stages fetch(F), decode(D), execute(E) and write(W). Different instruction spent different number of clock cycles.
The value in the box represents clock cycles taken by instructions in different states.
At what clock cycle, instruction I3, will complete its decoding?
(a) 6th clock cycle (b) 7th clock cycle
(c) 12th clock cycle (d) 13th clock cycle
Solution: Option (b)
Explanation:

At 7th clock cycle I3 will complete its decoding.

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Computer Science Junction: Computer Organization and Architecture - Practice Set 3 Solution
Computer Organization and Architecture - Practice Set 3 Solution
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