Computer organization and architecture based practice questions for gate exam :Computer Science Study Material for Gate

COMPUTER ORGANIZATION  ARCHITECTURE Practice Set 7 1. A program consists of four major types of instructions. The instr...


COMPUTER ORGANIZATION  ARCHITECTURE


Practice Set 7

1. A program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given in the following table.If the clock frequency of the processor is 400 MHz, what is the average CPI of the processor?

(a) 3.75 (b) 2.87
(c) 1.87 (d) 1.54

2. Which of the following best characterize computer that uses memory mapped I/O?

(a) the computer provides special instruction for manipulating I/O port
(b) I/O ports are placed at addresses on bus and are accessed just like other memory location
(c) to perform an I/O operation, it is sufficient to place the data in an address and call the channel
to perform the operation
(d) ports are reference only by memory mapped instruction of the computer and are located hard
wired memory location

3. Suppose after analyzing a new cache design, you discover that the cache has far too many conflict misses and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity?

(a) Slower cache access time (b) Increase index bits
(c) Increase block size (d) All of these

4. Identify the false statements:

S1: Separate I/O address space does not necessarily mean that I/O address lines are physically
separated.

S2: Address decoder is an essential part of I/O interface.

(a) Only S1 (b) Only S2
(c) Both S1 and S2 (d) Neither S1 nor S2

5. DMA interface unit eliminates the need to use CPU registers to transfers data from

(a) MAR to MBR (b) MBR to MAR
(c) I/O units to memory (d) Memory to I/O units

6. Compared to RISC processors, CISC processors contain _________.
(a) More registers and smaller instruction set
(b) Larger instruction set and less registers
(c) Less registers and smaller instruction set
(d) More transistor elements

7. Which of the following miss is definite to occur in cache memory?
(a) Cold-start miss (b) Capacity miss
(c) Conflict miss (d) All of these

8. Which of the following are not considered as part of I/O interface which connects bus and I/O device?

(i) Address decoder
(ii) Control circuitry
(iii) Data and status register

(a) Only (i) and (iii) (b) Only (ii) and (iii)
(c) (i), (ii) and (iii) (d) None of these

9. A two way set associative cache has lines of 16 byte and a total cache size of 8 K bytes. The 256 M byte main memory is byte addressable. Which one of the following main memory block is mapped on to the set ‘0’ of the cache memory?

(a) (CFED09B)16 (b) (FCED90C)16

(c) (CFED00B)16 (d) (FECD10C)16

10. Consider the following statements:

1. Time taken for a single instruction on a pipelined CPU is less than or equal to time taken on a
non-pipelined (identical) CPU.

2. In a uniform delay pipeline execution time for a single instruction is equal to the execution
time in non-pipelined processor. (Assume no buffer delay)

Which of the above statement(s) is correct?

(a) Only 1 (b) Only 2
(c) Both 1 and 2 (d) Neither 1 nor 2

11. Suppose the cache memory is 100 times faster than main memory and it is used 50% of the time. The performance is gained by introducing this cache is __________.

12. Consider a 16 bit processor in which the following one address instruction is loaded in main memory.

The effective address using PC relative addressing mode when processor is executing an instruction at location 300 is _________.

13. The number of micro-operations required to fetch an instruction from memory is __________.

14. The minimum size of the ROM which maintains truth table of square of 3 bit numbers is __________ (in bits).

15. Consider a cache with 64 blocks and block size of 16 bits. The block number of byte address 1600 is __________.

16. Consider a 5 stage pipeline with IF, ID, EX, MEM and WB latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made 50% faster, the percentage it will improve the performance CPU is __________.

17. A certain architecture supports indirect, direct and register addressing modes for use in identifying operands for arithmetic instructions. Which of the following cannot be achieved with a single instruction?

(a) specifying a register number in the instruction such that the register contains the value of an
operand that will be used by the operation.
(b) specifying a register number in the instruction such that the register will serve as the
destination for the operation’s output.
(c) specifying an operand value in the instruction such that the value will be used by the
operation.
(d) specifying a memory location in the instruction such that the memory location contains the
value of an operand that will be used by the operation.





18. Consider a system in which DMA technique is used to transfer 16 MB of data from an I/O device into memory. The bandwidth of I/O device is 128 KB/s. What percentage of time is the CPU in busy mode (approximately)?

(a) 17 (b) 82
(c) 35 (d) 41

19. Consider a 5 stage instruction pipeline having latencies (in ns) 1, 2, 3, 4 and 5 respectively. Find average CPI of non-pipeline CPU when speed up achieved with respect to pipeline is 4 (assume ideal case for pipelining)?

(a) 1.23 (b) 1.33
(c) 1.66 (d) 1.73

20. A Hypothetical control unit supports 5 groups of mutually exclusive signals

Find size of control memory (in bytes) using vertical programming if control unit support 256 control word memory.

(a) 704 bytes (b) 672 bytes
(c) 604 bytes (d) 804 bytes

21. A system supports 2 address and 1 address instructions only. A 32 bit instruction is stored in 16 K words memory. What will be the number of one address instructions supported by this system when there are 12 two address instructions?

(a) 16 K (b) 32 K
(c) 64 K (d) 128 K

22. An instruction pipeline consist of 4 stages IF, ID, EX and WB. Four instructions need these stages for different number of cycles as shown by the table below .Find number of clock cycles needed to execute the above 4 instructions.

(a) 12 (b) 13
(c) 14 (d) 15

23. The main memory of a computer has 2×10×20 blocks while the cache has 2×10 blocks. If the cache uses the set associative mapping scheme with two blocks per set, then block 232 of main memory maps to set X. What is the value of X?

(a) 12 (b) 24
(c) 2 (d) 42





24. Consider the addition of the two numbers 10001110 and 10000000 in an 8-bit ALU. Which of the following best summarizes the result and the status of the Z(zero), S(sin), C(carry) and O(overflow) flags? Assume that the numbers are represented in 2’s Complement format and that S=1 if the result is negative.

(a) Sum = 100001110, Z = 0, C = 1, O = 0, S = 1
(b) Sum = 00001110, Z = 0, C = 0, O = 1, S = 0
(c) Sum = 10000110, Z = 0, C = 0, O = 1, S = 0
(d) Sum = 100001110, Z = 0, C = 1, O = 1, S = 0

25. Consider a CPU shared bus system in which each CPU requests the bus 35% of the time. What is the probability that exactly 3 CPU’s are requesting the bus, when there are 10 CPU’s competing for bus?
(a) 0.40 (b) 0.25
(c) 0.35 (d) 0.15

26. Consider a 4 way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates 20 bit addresses for words in main memory.

Match the following main memory addresses with the set number.
List-I List-II
A. 1111 0101 1010 0011 1111 1. 16
B. 0000 1111 1100 0011 0011 2. 10
C. 1100 1100 1100 1100 0011 3. 8
D. 1010 1010 1010 1010 1010 4. 19
Codes:
A B C D
a. 3 1 4 2
b. 3 1 2 4
c. 3 2 4 1
d. 2 3 1 4
(a) a (b) b
(c) c (d) d

27. During a program execution out of 1000 memory references there are 250 and 120 misses in L1 (Level-1) and L2 (Level-2) caches respectively. Hit times for L1 and L2 cache are 24 and 40 cycles respectively. If there are 2.5 memory references per instruction, how many averages stall cycles per instruction? (Assume L2 to memory miss penalty is 250 cycles)
(a) 50 (b) 100
(c) 150 (d) 200

28. Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096. Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192. Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
A[i] = A[i] + B[2 * i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-through policy?
(a) 0 (b) 256
(c) 1,024 (d) 2,048

29. Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size
I1 MOV CX,0005 ; CX ← 0005
I2 MOV BX,OFF7H ; BX ← OFF7H
I3 MOV AX,OBCAH ; AX ← OBCAH
I4 OR BX,AX ; BX ← BX (OR) AX
I5 AND DX,AX ; DX ← DX (AND) AX
I6 LOOP I3 ; LOOP till CX = 0
Processor clock frequency is 1 MHz. In which data transfer operations takes 6 cycles, data manipulation operations takes 4 cycles and transfer of control operations takes 2 cycles to execute. The time is required to execute the program is _________ (in ╬╝sec).

30. A 17 way set associative cache has 16 byte blocks and 32 bit byte addressable memory. The cache size is 17408 bytes. The total bits required for both tag and word offset for any CPU reference is __________.

31. Consider a pipeline ‘x’ consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeline ‘y’ contain the same number of stages but EX stage is divided into 4 sub stages, (EX1, EX2, EX3 and EX4) with equal delay i.e. (8 ns/4) and ID stage is divided into 2 substages (ID1 and ID2) with equal delays of (5 ns/2). In the pipeline x and y memory reference instructions are not overlapped so the penalty of memory reference instructions in the pipeline ‘x’ is 4 cycles and in the pipeline ‘y’ is 8 cycles. If the program contains 30% of the instructions which are memory based instructions, the speedup ratio of x is speedup ratio of y is ___________.

32. Consider execution of 100 instructions on a 5 stage pipeline. Let P be the probability of an instruction being a branch. The value of P such that speed up is atleast 4 is __________. (Assume each stage takes 1 cycle to perform it’s task and branch is predicted on fourth stage of the pipeline).

33. A machine has 24 bit instruction format. It has 32 registers and each of which is 32 bit long. It needs to support 49 instructions. Each instruction has two register operands and one immediate operand. If the immediate operand is signed integer, the minimum value of immediate operand is _________.

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