Computer architecture based practice questions for gate exam-Computer Science Study Material for Gate

 Practice Questions  for Gate Exam   Practice SET 1 1 . A memory system consisting of two levels L1 and L2. The required access ti...


 Practice Questions  for Gate Exam


  Practice SET 1


1. A memory system consisting of two levels L1 and L2. The required access times of those are 5 ns and 120 ns respectively. Another memory system has also two levels L3 and L4 whose access time are 10 ns and 150 ns respectively. The hit ratio of second system is 0.8 and average access time is twice than that of first system. What is the hit ratio of first system?
(a) 0.38 (b) 0.5
(c) 0.75 (d) 0.87

2. A two level memory system has levels with access time T1 = 15 ns and T2 = 200 ns. The hit ratio for this system is 0.9. If hit ratio is made to 1 then what will be the new value of T1?
(a) 10 ns (b) 15 ns
(c) 20 ns (d) 25 ns

3. In the above case if average access time is increased by 15%. What will be the change in hit ratio?
(a) 3% decrease (b) 3% increase
(c) 5% decrease (d) 5% increase

4. A cache has used a word from a memory block ranged between 0 – 63. If the same word is required soon then it will exploit

(a) Spatial locality of reference (b) Temporal locality of reference
(c) Capacity miss (d) None of the above

5. A direct mapped cache is of size 64 KB with block size 32 Bytes. Logical address generated is 32 bit. What is the bits required for tag and block field?
(a) 16, 11 (b) 21, 11
(c) 16, 16 (d) 16, 6

6. Consider a cache with 128 blocks of 16-words each. CPU generates 16 bit address. What is the tag size if 4-way Set associative mapping is used?
(a) 6 (b) 7
(c) 8 (d) 9

                                       



7. A cache uses 8-way set associative mapping. The number of blocks in the cache is 256, each of size 16 words. Main memory is 16 bit. What is the number of tag comparison required?
(a) 8 (b) 32
(c) 128 (d) 256

8. Consider a direct mapped cache with 8 cache blocks (0 – 7). If the memory blocks required are in order (2, 5, 15, 1, 8, 4, 0, 16, 19, 2, 13, 25, 18, 30, 24, 0, 67, 35, 5, 25). What is the hit ratio?
(a) 0 (b) 1/10
(c) 1/2 (d) 9/10

9. Consider a fully associative cache with 8 cache blocks (0 – 7) and the following sequence of memory block request arrives (3, 6, 12, 17, 5, 13, 45, 3, 12, 24, 17, 20, 28, 45, 3, 27, 64, 6, 20, 12). If LRU is used in which cache block the memory block 12 will reside?
(a) 2 (b) 3
(c) 5 (d) 6

10. Consider a 2-way set associative mapping is used where there are 8 cache blocks (0 – 7). If LRU is used to replace the memory blocks (0, 4, 9, 5, 16, 13, 15, 19, 25, 63, 24) then what is the number of blocks present in cache after end of sequence?
(a) 5 (b) 6
(c) 7 (d) 8

11. Consider an array of 4 elements and each element occupies 4-words. A 16 word cache is used and divided into a block of 8 words. If the following code is executed what is the hit ratio?

for (i = 0; i < 2; i++)
for (j = 0; j < 2; j++)
x = A[i, j] + A[j, i]
(a) 0.5 (b) 0.66
(c) 0.75 (d) 0.87

12. Consider a system with cache access time 20 ns and main memory access time 140 ns. If 60% operations are read operations and hit ratio is 90%, what is the effective access time if write through updation technique is used?

(a) 75.2 ns (b) 76.4 ns

(c) 83.2 ns (d) 84.4 ns




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