COMPUTER ORGANIZATION AND ARCHITECTURE

Practice Set 6


Practice These Questions



1. Consider the following statements.

S1: The RISC processor has CPI always 1.
S2: In horizontal instruction control signals are always in encoded form.
S3: In vertical instruction control signals are always in encoded form.
S4: In terms of speed vertical instruction is slower than horizontal instruction.

Which of the above statements are true?

(a) Only S1 and S2 (b) Only S2 and S3
(c) Only S1, S3 and S4 (d) None of the above

2. Computer uses addressing mode technique for __________.

(a) giving program versatility to user by providing facilities as a pointer to memory counters for
loop control
(b) reducing number of bits in the field of instruction
(c) specifying rules for modifying or interpreting address field of the instruction
(d) All of the above

3. Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory?
(a) Reference bit (b) Dirty bit
(c) Tag bit (d) Valid bit

4. Match List-I with List-II and select the correct answer using the codes given below the lists:
List-I List-II
A. Pointer 1. Indirect addressing mode
B. Position independent code 2. Immediate addressing mode
C. Constant operand 3. Relative addressing mode

Codes:
A B C
(a) 1 2 3
(b) 3 2 1
(c) 1 3 2
(d) 2 3 1

5. A 50 kbps device is connected to the processor. The interrupt overhead is 50 μsec. The minimum performance achieved when interrupt initiated and data transferred is used instead of programmed I/O is __________.
(a) 2.4 (b) 0.4
(c) 3 (d) 3.5

6. Consider the following sequence of micro-operations.
MBR ‹ PC
MAR ‹ SP
M[MAR] ‹ MBR
PC ‹ Vector address.
Which of the following operation performed by this sequence?
(a) Instruction fetch (b) Operand fetch
(c) Interrupt subprogram initialization (d) Conditional branch

7. We have two designs P1 and P2 for a synchronous pipeline processor. P1 has 8 pipeline stages with execution time of 3 nsec, 2 nsec, 4 nsec, 8 nsec, 2 nsec, 5 nsec, 4 nsec and 1 nsec while design P2 has 5 stages each with 5 nsec each with 5 nsec execution time. How much time (in μsec) can be saved using design P2 over design P1 for executing 500 instructions? (upto 3 digit).
(a) 2.536 (b) 1.365
(c) 1.536 (d) 1.653

8. In which of the following addressing mode, the content of the program counter is added to the address part of the instruction to get the effective address?

(a) Indexed addressing mode (b) Implied addressing mode
(c) Relative addressing mode (d) Register addressing mode

9. Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is __________.
(a) 2.16 (b) 3.16
(c) 4.20 (d) 4.16

10. If the last operation performed on a computer with an 8-bit word has an addition in which the two operands were 00000010 and 00000011, what would be the value of the Overflow, Sign and Half-Carry flags respectively?
(a) 0, 0, 0 (b) 0, 1, 0
(c) 1, 0, 1 (d) 0, 1, 1

11. A 4 byte long PC-relative branch instruction is fetched from memory address 51210 and while its execution, the branch is made to location 88510. What is the unsigned displacement present in the instruction? (relative value)



                   

12. Consider the following program segment:
Instruction Meaning Size (words)
I1 LOAD r0, 500 r0 ⃪ [500] 2
I2 MOV r1, r0 r1 ⃪ [r0] 1
I3 ADD ro, r1 r0 ⃪ r0 + r1 1
I4 INC r0 r0 ⃪ r0 + 1 1
I5 INC r1 r1 ⃪ r1 + 1 1
I6 ADD r0, r1 r0 ⃪ r0 + r1 1
I7 Store r1, r0 M[(r1)] ⃪ r0 2
I8 Halt Stop 1

Assume that memory is word addressable with word size 32 bits. Program is loaded into memory location (3000)10 onwards. The value of PC at the end of execution of above program is __________.

13. A branch mark program is running on a 40 MHz processor. The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count.
Instruction Type Instruction Count Cycles per Instruction
Integer arithmetic 45000 1
Date transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

The execution time in msec is __________.

14. A hypothetical control unit supports 5 groups of mutually exclusive control signals. The numbers of bits that can be saved using vertical approach compared to horizontal are __________.

15. Consider the micro-programmed control unit which support 256 instructions, each of which on an average takes 16 micro operations. The system support 16 flag conditions and 52 control signals. If vertical microprogramming control is used in the system then total length of control word is __________ (bits/word).

16. Consider a non-pipeline processor has clock rate of 25 MHz and CPI of 6, another processor designed with same clock rate and 8 stage instruction pipeline. If program containing 500 instructions is executed on both processors, then the speedup factor is __________.

17. Consider the following statements:
S1: Compulsory miss can be reduced.
S2: Conflict miss can be reduced.
S3: Capacity miss can be reduced.
Which of the above statements are True?
(a) Only S1 (b) Only S1 and S2

(c) Only S2 and S3 (d) S1, S2 and S3

18. Consider the hypothetical processor which support 512 k words memory. It uses the memory mapped IO configuration. In which when 2 MSB bits of address are 1 then assigned to IO port.
How many numbers of I/O port address and memory addresses are possible in the processor respectively?
(a) 1×217, 3×217 (b) 3×217, 1×217
(c) 2×217, 1×217 (d) None of these

19. Which of the following statements are True?
S1: Reference bit in page table entry used for page replacement.
S2: In hierarchical memory access organization, CPU perform read and write operation on only
level 1 memory.
S3: In simultaneous memory access organization, CPU perform read and write operation on any
level of memory.
(a) S1 and S2 only (b) S1 and S3 only
(c) S2 and S3 only (d) S1, S2 and S3

20. A computer has 32-bit instruction and 9-bit address. If there are 400 two address instructions then how many one address instructions can be formulated?
(a) 214 (b) 232 – 200
(c) 214 – 400 (d) (214 – 400) × 29

21. Which of the following is true?
(a) In write through protocol, cache location and main memory location are updated
simultaneously.
(b) In write back protocol, cache location and main memory location are updated simultaneously.
(c) Modified or dirty bits are used by write through protocol.
(d) None of these.

22. A 16KB 4-way set associative write-back cache is organized as multiple blocks, each of size 64-bytes.The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising with 1 valid bit and 1 Modified bit.
As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
(a) 5362 bytes (b) 5361 bytes
(c) 704 bytes (d) 176 bytes

23. Consider a system with the main memory access time as 200 ns and cache access time as 10 ns. Hit ratio for read request is 0.8 and 80% of the memory requests are for read. If write through policy is used, then the average time considering both read and write requests is __________.
(a) 169.6 ns (b) 192.4 ns
(c) 78.4 ns (d) None of these

24. Consider the following instructions.
I1 : R1 = 100
I2 : R1 = R2 + R4
I3 : R2 = R4 + 25
I4 : R4 = R1 + R3
I5 : R1 = R1 + 30
Calculate sum of (WAR, RAW and WAW) dependencies the above instructions.
(a) 10 (b) 12
(c) 6 (d) 8


                                 
25. A 4-way set associative cache memory consists of 128 blocks. The main memory consists of 32768 memory blocks and each block contains 512 eight bit words. Find how many bits are needed to represent TAG, SET and WORD field respectively?
(a) 5, 9, 10 (b) 10, 6, 8
(c) 10, 9, 5 (d) 10, 5, 9

26. Suppose directed mapped cache with 2m lines 2p bytes per cache lines. Memory is byte addressable of 2n bytes. Compute the space required for storing tags (in bits)?
(a) 2n – (m+p) (b) 2m × (n – (m+p))
(c) 2n+m (d) (m+n) × 2m

27. Consider a small two-way set-associative cache memory, consisting of 4 blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the sequence of block addresses 18, 22, 10, 22, 18 is __________.
(a) 2 (b) 3
(c) 4 (d) 5

28. Consider a pipelined system with four stages: IF, ID, EX, WB. Following chart shows the clock cycles required by each instruction to compete each stage
How many clock cycles are required to complete the above instructions?
(a) 15 (b) 9
(c) 14 (d) 13

29. A computer has a cache, main memory and a hard disk used for virtual memory. If referenced word is in cache, 20 ns are required to access it. If it is in main memory but not in cache 60 ns are needed to load it into cache and then reference is started again. If word is not in main memory, 12 ms are required to fetch the word from disk followed by 60 ns to copy into cache, the reference is started again. The cache hit ratio is 0.9 and main memory hit ratio is 0.6.
The average time in nano seconds required to access a referenced word on this system is ___________.

30. In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by 20%. The overall speedup achieved if the ratio of the number of fixed point operation to floating point operations is 4 : 6 and the floating point operation used to take twice the time taken by fixed point operation in the original design (upto 2 decimal places) is __________.

31. Suppose that in 1000 memory references there are 150 misses in first level and 100 miss in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles.If there are 4 memory references per instruction, the average stall per instruction is ___________.

32. Consider the machine with a byte addressable main memory of 216 byte, block size of 16 byte and a 2 way set associative mapped cache having 210 lines. Suppose there are two bytes in main memory i.e. first byte [E 01 F]16 and second byte [E 208]16 respectively then the difference of the set value (in decimal) between given two bytes i.e. (SET value of second byte – SET value of 1st byte) is __________.

33. Consider two cache organizations. The first one if 64 KB way associative with 64 byte block size. The second one is of the 64 KB direct mapped cache. The size of an address is 32 bits in both organizations. A 4 to 1 multiplexer has latency of 0.8 ns which k bit comparator has latency of k/5 nsec. The difference between the hit latencies of both cache organizations (i.e. associative hit latency – direct mapped hit latency) (in nsec) is ___________.


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