Practice Set 3

(Instruction Pipelining, Cache & Main memory, Secondary Storage)

1. More than one word is put in one cache block to
(a) Exploit temporal locality references in a program
(b) Exploit spatial locality references in a program
(c) Reduce miss penalty
(d) All of these

2. A pipeline P is found to provide a speedup of 6.16 when operating at 100 MHz and an efficiency of 88 percent. How many stages does P have?

3. How big is a four way set associative cache memory with a block size of 64 Bytes and containing 1024 sets?

4. A five stage pipeline has a clock cycle time of 5ns. If the non-pipeline clock is also of the same duration than what is the speed up for 75% of pipeline efficiency?

5. A tiny bootstrap loader program is situated in
(a) Hard disk (b) ROM
(c) BIOS (d) None of these

6. If a cache access requires one clock cycle and handling cache misses stalls the processor for an additional five cycles, which of the following cache hit rates comes closest to achieving an average memory access of 2 cycles (in %)?

7. Cache and word addressable main memory system has the following specification
Cache block size = 16 words
Set size = 2 blocks

Number of sets = 128
Number of bits in a word = 32 bits
Cache access time (Tc) = 20ns
Memory access (Tm) = 120ns
Hit (H) = 0.8
Size of main memory address = 21bits
What is the total cache size needed?
(a) (16k + 140) bytes (b) (16k + 320) bytes
(c) (256k + 180) bytes (d) (60k + 300) bytes

8. Consider a machine with 10ns clock and it takes 4 clock cycle per ALU instruction, 5 clock cycle per branch instruction, 6 clock cycle memory instruction. There exists 40% ALU instruction, 20% branch instruction and 40% memory instruction.

What is throughput of pipeline system if overhead is 2ns?
(a) 83MIPS (b) 84MIPS
(c) 85MIPS (d) 86MIPS

9. A 5 stage pipeline has the stages IF, ID, OF, PO, WB (Assume that there are no separate data and instruction caches). For the program below, what is/are the hazard(s) possible? MOV R1,A; R1←μ[A]
MOV R2,A; R2←μ[B] ADD R1,R2; R1←R1+R2 MOV X,R1; μ[x]←R1
(a) Data Hazard (b) Structural Hazard
(c) Control Hazard (d) Both (a) &(b)

10. An instruction pipeline consists of 4 stages fetch(F), decode(D), execute(E) and write(W). Different instruction spent different number of clock cycles.

The value in the box represents clock cycles taken by instructions in different states.
At what clock cycle, instruction I3, will complete its decoding?
(a) 6th clock cycle (b) 7th clock cycle
(c) 12th clock cycle (d) 13th clock cycle

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