Paging Technique for Memory Management

Paging is a memory address scheme that permit physical address space of a process to be  non contiguous Paging avoids external fragmentation and need of Compaction. In Paging method physical memory space is divided in to fixed size blocks called frames and process logical memory space  is divided into block of the same size known as pages. Size of a page is equal to the size of a frame.

                      hardware support for paging

 Every address generated the CPU is divided into two parts: a page number {p) and a Page Offset(d) . The page number is used as an index into a The page table contains the base address of each page in physical memory. This base address is combined with the page offset to define the physical memory address that is sent to the memory unit. The paging model of memory is shown in figure.

Size of Logical Address and Physical Address

The page size (like the frame size) is defined by the hardware. The size of a page is typically a power of 2, varying between 512 bytes and 16 MB per page, depending on the computer architecture. The selection of a power of 2 as a page size makes the translation of a logical address into a page number and page offset particularly easy. If the size of the logical address space is 2m, and a page size is 2 addressing units (bytes or wordst then the high-order m- n bits of a logical address designate the page number, and the low-order bits designate the page offset. Thus, the logical address is as follows: 

paging technique of memory management

Where is an index into the page table and is the displacement within the page.

Example : consider the memory in Figure 8.9. Here, in the logical address, n= 2 and = 4. Using a page size of 4 bytes and a physical memory of 32 bytes (8 pages), we show how the user's view of memory can be mapped into physical memory. Logical address 0 is page 0, offset 0. Indexing into the page table, we find that page 0 is in frame 5. Thus, logical address 0 maps to physical address 20 [= (5 x 4) + 0]. Logical address 3 (page 0, offset 3) maps to physical address 23 [ = (5 x 4) + 3]. Logical address 4 is page 1, offset 0; according to the page table, page 1 is mapped to frame 6. Thus, logical address 4 maps to physical address 24 [ = ( 6 x 4) + 0]. Logical address 13 maps to physical address 9.

hardware support for paging technique

Figure 3 :  Hardware Support for Paging Technique.

Keywords: Introduction to paging technique, hardware support for paging, the logical address and physical address, page offset, page number, page size, calculation of logical address and physical address in memory.